A dynamic random access memory (DRAM) circuit includes an array of capacitive storage memory cells accessible through corresponding access transistors. Data stored in each memory cell is an electrical charge stored on a capacitor, which dissipates over time through various leakage paths of the DRAM circuit. Therefore, the information stored in the memory cells is usually periodically recharged (also known as “refreshed”) in order to retain the stored information. In some applications, a refresh control circuit of the DRAM circuit refreshes a row of memory cells every predetermined, fixed time intervals, and such predetermined time intervals is sometimes referred to as a refresh period of the DRAM circuit.